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MC10EP31, MC100EP31 3.3V / 5V ECL D Flip-Flop with Set and Reset
The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. The 100 Series contains temperature compensation.
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8 8 1 SO-8 D SUFFIX CASE 751 HEP31 ALYW 1 1 KEP31 ALYW 8
* 340 ps Typical Propagation Delay * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V *
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Open Input Default State
8 1 TSSOP-8 DT SUFFIX CASE 948R
8 HP31 ALYW 1
8 KP31 ALYW 1 L = Wafer Lot Y = Year W = Work Week
* * Q Output Will Default LOW with Inputs Open or at VEE
H = MC10 K = MC100 A = Assembly Location
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC10EP31D MC10EP31DR2 MC100EP31D MC100EP31DR2 MC10EP31DT MC10EP31DTR2 MC100EP31DT Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel
MC100EP31DTR2 TSSOP-8
(c) Semiconductor Components Industries, LLC, 2001
1
April, 2001 - Rev. 5
Publication Order Number: MC10EP31/D
MC10EP31, MC100EP31
PIN DESCRIPTION
PIN SET 1 8 VCC CLK* Reset* Set* S D 2 D Flip Flop CLK 3 R 6 Q 7 Q D* Q, Q VCC VEE FUNCTION ECL Clock Inputs ECL Asynchronous Reset ECL Asynchronous Set ECL Data Input ECL Data Outputs Positive Supply Negative Supply
* Pins will default LOW when left open.
TRUTH TABLE
RESET 4 5 VEE D L H X X X SET L L H L H RESET L L L H H CLK Z Z X X X Q L H H L UNDEF
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Z = LOW to HIGH Transition
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW N/A > 4 kV > 200 V > 2 kV Level 1 UL-94 code V-0 A 1/8" 28 to 34 75 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1.) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2.)
Symbol VCC VEE VI Iout TA Tstg JA JC JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA C C C/W C/W C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
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MC10EP31, MC100EP31
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4.) Output LOW Voltage (Note 4.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 2165 1365 2090 1365 Typ 34 2240 1490 Max 44 2415 1615 2415 1690 150 0.5 Min 26 2230 1430 2155 1430 25C Typ 35 2355 1555 Max 45 2480 1680 2480 1755 150 0.5 Min 28 2290 1490 2215 1490 85C Typ 37 2415 1615 Max 47 2540 1740 2540 1815 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 6.) Output LOW Voltage (Note 6.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 3865 3065 3790 3065 Typ 34 3940 3190 Max 44 4115 3315 4115 3390 150 0.5 Min 26 3930 3130 3855 3130 25C Typ 35 4055 3255 Max 45 4180 3380 4180 3455 150 0.5 Min 28 3990 3190 3915 3190 85C Typ 37 4115 3315 Max 47 4240 3440 4240 3515 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 6. All loading with 50 ohms to VCC-2.0 volts.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 7.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 8.) Output LOW Voltage (Note 8.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 -1135 -1935 -1210 -1935 Typ 34 -1060 -1810 Max 44 -885 -1685 -885 -1610 150 0.5 Min 26 -1070 -1870 -1145 -1870 25C Typ 35 -945 -1745 Max 45 -820 -1620 -820 -1545 150 0.5 Min 28 -1010 -1810 -1085 -1810 85C Typ 37 -885 -1685 Max 47 -760 -1560 -760 -1485 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. 8. All loading with 50 ohms to VCC-2.0 volts.
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MC10EP31, MC100EP31
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 9.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10.) Output LOW Voltage (Note 10.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 2155 1355 2075 1355 Typ 34 2280 1480 Max 44 2405 1605 2420 1675 150 0.5 Min 26 2155 1355 2075 1355 25C Typ 35 2280 1480 Max 45 2405 1605 2420 1675 150 0.5 Min 28 2155 1355 2075 1355 85C Typ 37 2280 1480 Max 47 2405 1605 2420 1675 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 10. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 11.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 12.) Output LOW Voltage (Note 12.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 3855 3055 3775 3055 Typ 34 3980 3180 Max 44 4105 3305 4120 3375 150 0.5 Min 26 3855 3055 3775 3055 25C Typ 35 3980 3180 Max 45 4105 3305 4120 3375 150 0.5 Min 28 3855 3055 3775 3055 85C Typ 37 3980 3180 Max 47 4105 3305 4120 3375 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 12. All loading with 50 ohms to VCC-2.0 volts.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 13.)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 14.) Output LOW Voltage (Note 14.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Input HIGH Current Input LOW Current 0.5 Min 26 -1145 -1945 -1225 -1945 Typ 34 -1020 -1820 Max 44 -895 -1695 -880 -1625 150 0.5 Min 26 -1145 -1945 -1225 -1945 25C Typ 35 -1020 -1820 Max 45 -895 -1695 -880 -1625 150 0.5 Min 28 -1145 -1945 -1225 -1945 85C Typ 37 -1020 -1820 Max 47 -895 -1695 -880 -1625 150 Unit mA mV mV mV mV A A
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 13. Input and output parameters vary 1:1 with VCC. 14. All loading with 50 ohms to VCC-2.0 volts.
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MC10EP31, MC100EP31
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15.)
-40C Symbol fmax tPLH, tPHL Characteristic Maximum Frequency (See Figure 2. Fmax/JITTER) Propagation Delay to Output Differential CLK to Q, Q S, R to Q, Q tRR tS tH tPW tJITTER tr tf Set/Reset Recovery Setup Time Hold Time Minimum Pulse width SET, RESET Cycle-to-Cycle Jitter (See Figure 2. Fmax/JITTER) Output Rise/Fall Times (20% - 80%) Q, Q 50 550 450 0.2 120 <1 180 60 550 450 0.2 130 <1 200 70 550 450 0.2 150 <1 220 ps ps 250 300 225 100 150 330 380 400 450 270 330 225 100 150 340 400 410 470 300 360 225 100 150 370 430 440 500 ps ps ps Min Typ >3 Max Min 25C Typ >3 Max Min 85C Typ >3 Max Unit GHz ps
15. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC-2.0 V.
1100 1000 900 VOUTpp (mV) 800 700 600 500 400 300 200
11 10 JITTEROUT ps (RMS) 9 8 7 6 5 4 3 2 1 4000 5000 6000 (JITTER) 3000
EEEEEEEEE EEEEEEEEE
0 0 1000 2000
100
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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EE EE
MC10EP31, MC100EP31
Q Driver Device Qb 50 W 50 W
D Receiver Device Db
V TT V TT = V CC - 2.0 V
Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020
- - - - - - - - - - -
ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC10EP31, MC100EP31
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE W
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A
8x
K REF 0.10 (0.004)
M
0.15 (0.006) T U
S 2X
TU
S
V
S
L/2
8
5
L
1 PIN 1 IDENT 4
B -U-
0.25 (0.010) M
0.15 (0.006) T U
S
A -V-
F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_
C 0.10 (0.004) -T- SEATING
PLANE
D
-W- G DETAIL E
DIM A B C D F G K L M
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MC10EP31, MC100EP31
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MC10EP31/D

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